In electronic device implementations, it is often necessary to transfer information synchronously between different components. Such a situation may arise, for example, when transferring data between several chips or between several blocks on a chip. Because each component typically runs off of its own internal clock signal, synchronous information transfer is usually achieved by providing a reference clock signal to each of the components and then having each of the components synchronize its internal clock signal with the reference clock signal. Once synchronization is achieved, the components perform the information transfer using their own internal clock signals.
To synchronize a component's internal clock signal with a reference clock signal, a phase lock loop (PLL) is often used. A typical PLL is shown in FIG. 1, wherein the PLL 110 comprises a phase frequency detector (PFD) 112, a charge pump 114, a loop filter 116, and a voltage controlled oscillator (VCO) 118. The internally generated clock signal DCLK and the reference clock signal RCLK are fed as inputs to the PFD 112. The function of the PFD 112 is to detect the difference in phase and frequency between the two clock signals, and to generate output control signals UP and DOWN indicative of the phase and frequency differences. These control signals UP, DOWN are then fed as inputs to the charge pump 114. In response, the charge pump 114 generates a net current in accordance with the input control signals UP, DOWN, to either charge or discharge the loop filter 116 to a particular voltage. It is the voltage on loop filter 116 that controls the frequency of the DCLK generated by VCO 118. Preferably, the voltage present at the input of the VCO 118 is such that it causes the VCO 118 to generate a new DCLK signal having a frequency and phase closer to that of the reference signal RCLK. In this manner, the PLL 110 "pushes" DCLK towards RCLK.
Once the new DCLK is generated, it is fed back to the input of the PFD 112 along with RCLK and the process is repeated. Because of the feedback loop, this adjustment process continues until DCLK "locks on" to RCLK in both phase and frequency. In some implementations, it is desirable for DCLK to have a frequency that is a multiple of the RCLK frequency. In such implementations, a modulo n feedback counter 120 is inserted into the feedback path as shown. If a counter 120 is used, a corresponding delay element 122 having the same delay as the counter is usually imposed between RCLK and the input of the PFD 112 to equalize signal delays.
Once DCLK locks on to RCLK, the two signals will be completely in phase. As a result, the outputs UP, DOWN of PFD 112 will indicate that there is no phase difference. This condition typically is manifested by the UP and DOWN control signals having the same pulse width. In response to the input control signals having the same pulse width, the charge pump 114 ideally outputs a net current of zero so that no further charge is injected into the loop filter 116, thereby maintaining the overall loop in locked condition. In order to achieve this, however, the charge pump 114 is required to source and sink the same amount of current. Because a charge pump typically contains both PMOS and NMOS devices, and because these types of devices have mobility and capacitance differences, sourcing and sinking the same amount of current given equal control pulse widths is very difficult to do. If the charge pump 114 is unable to generate zero net current for control signals having equal pulse widths, the PLL 110 will be forced to maintain unequal pulse widths in the UP and DOWN control signals to obtain zero net current from the charge pump. To have unequal pulse widths in the UP and DOWN control signals, a phase difference needs to exist between the DCLK and the RCLK signals. This phase difference in turn causes clock skew to be imposed on the inputs of the PFD 112, a very undesirable result. To overcome this problem, what is needed is a charge pump that is capable of generating substantially zero net current given input control signals having substantially identical pulse widths.